Due to process and device development limitations, a sampling frequency of a single Analog to Digital Converter (ADC) chip cannot be very high, and a higher sampling frequency may be implemented by means of interlaced sampling, driven by sampling clocks at different phases, of multiple ADC chips.
The sampling clocks at the different phases are generally implemented by using the following solution: A logic circuit divides a clock source signal into n channels to obtain n channels of signals whose frequencies are equal to a frequency of the clock source signal divided by n and whose phases are different from each other, where n≥2 and n is an integer; and different quantities of phase inverters are respectively connected in series in transmission channels of the n channels of signals to perform delaying, so as to obtain n channels of sampling clocks, and sampling points of interlaced sampling driven by the n channels of sampling clocks are the same as sampling points of sampling driven by the clock source signal.
In a process of implementing the present application, the inventor finds that the prior art has at least the following problems:
Based on the process limitations, features of devices in the logic circuit cannot reach theoretical features, which causes a timing offset in picoseconds (ps) between sampling points of the n channels of sampling clocks obtained by using the logic circuit and sampling points of the clock source signal. Because a delay of the phase inverters connected in series in the transmission channels can be only as low as 20 ps, and the timing offset between the sampling points cannot be effectively adjusted, the interlaced sampling, driven by the n channels of sampling clocks, of the multiple ADC chips is non-uniform sampling, harmonic occurs in a signal obtained after analog-to-digital conversion, and conversion precision of the ADC is reduced.